1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates to a fully depleted silicon-on-insulator (SOI) device which includes an intrinsic channel region and a mechanism for tuning the threshold voltage thereof.
2. Description of the Related Art
Silicon-on-insulator (SOI) devices are characterized by structures in which the Si device layers are formed over an insulating film. FIG. 1 illustrates an exemplary configuration of such a device.
The device of FIG. 1 includes an nfet 102 and a pfet 104 formed within a layer 106. The layer 106 is located along an oxide layer 108 formed atop a p+ bulk material 110. The nfet 102 includes source and drain n-regions 112 and 114, a p-region 116, and a gate electrode 118. Likewise, the pfet 104 includes source and drain p-regions 120 and 122, an n-region 124, and a gate electrode 126. SOI devices of this type are characterized by low parasitic capacitances, as well as high dielectric isolation of the on-chip components.
A "partially depleted" SOI device refers to a structure in which the depletion region of the transistors does not extend all the way down to the oxide layer 108. An example of this is shown in FIG. 2. Here, the silicon layer 206 is of sufficient thickness and the n-regions 212 and 214 are appropriately configured (e.g., through use of source-drain extensions) such that the depletion region 228 is spaced from the upper surface of the oxide layer 208, i.e., only a portion of the p-region 216 is depleted.
A mechanism is known in the art for reducing thresholds in partially depleted SOI devices. Referring again to FIG. 2, a body contact 230 is embedded in the p-region 216, below the depletion region 228. Also, as shown, the body contact 230 is electrically tied to the gate electrode 218. As such, when the gate potential is turned on, the potential of the p-region 216 below the depletion region 228 (i.e., the "bulk region") is pulled up, whereby the bulk potential of the device tracks the gate potential. This results in a forward biasing of the bulk which in turn decreases the threshold voltage of the device.
A "fully depleted" SOI device is shown in FIG. 3. Here, the device is configured such that the depletion regions 328 extend completely down to the interface with the oxide layer 308. This is done, for example, by making the layer 306 much thinner than the corresponding layer 206 of the partially depleted device shown in FIG. 2. The structure is otherwise similar to that of the partially depleted device, and includes an nfet 302 having source and drain n-regions 312 and 314, a p-type channel region 316, and a gate 318, and a pfet 304 having source and drain p-regions 320 and 322, an n-type channel region 324, and a gate 326. The substrate 310 is tied to a fixed potential such as ground.
There are a number of factors which contribute to the magnitude of an SOI device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolt. Further, dimensional variations, charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations.
In this regard, it is noted that the partially depleted structure can be made tunable by providing isolated ohmic contacts to the bulk contact 216 and to the gate 218 shown in FIG. 2. For example, by monitoring leakage of a test transistor, the bias potential of the bulk material can be dynamically adjusted to maintain the desired threshold voltage. This approach, however, is not feasible in the fully depleted structure since the depletion region extends fully to the oxide layer, thus prohibiting the insertion of a bulk contact between the source and drain regions. Moreover, as the p+ substrate (reference numeral 310 in FIG. 3) extends fully beneath both the nfets and the pfets, adjusting the potential of the p+ substrate is not an effective means for tuning the threshold voltages of the devices. That is, there is no practical way in the structure of FIG. 3 to electrically isolate the respective bias potentials applied to nfets and pfets.
To overcome this problem, the SOI AS structure shown in FIG. 4 has been proposed. This device is characterized by the insertion of an insulative layer 430 of polysilicon between oxide layers 408a and 408b, with the oxide layer 408b being formed over the p+ substrate 410. Using masking techniques, the polysilicon is selectively doped to form conductive regions 432 and 434 beneath the nfet 402 (having n-type source and drains regions 412 and 414, a p-type channel region 416, and a gate 418) and the pfet 404 (having p-type source and drains regions 420 and 422, an n-type channel region 424, and a gate 426), respectively. Since the polysilicon is an insulator, the conductive regions 432 and 434 are electrically isolated. By providing isolated contacts 436 and 438 in the conductive regions 432 and 434, respectively, separate bias potentials can be applied to the nfet 402 and pfet 404, thereby tuning the threshold voltage of each device. The primary drawback of this approach, however, resides in the fact that an extra layer (i.e., the polysilicon layer 430) must be fabricated in the device.
Another configuration that has been proposed is shown in FIG. 5. Here, a first buried back gate p+ well 540 is formed within a p- substrate 510 beneath the nfet 518 (having n-type source and drain regions 512 and 514, a p-type channel region 516, and a gate 518), and a second buried back gate n+ well 542 is formed within the p- substrate beneath the pfet 504 (having p-type source and drains regions 520 and 522, an n-type channel region 524, and a gate 526). By providing separate contacts 544 and 546 in the conductive regions 540 and 542, respectively, separate bias potentials can be applied to the nfet 502 and pfet 504, thereby tuning the threshold voltage of each device. This approach has the advantage of avoiding the extra layers needed for the SOI AS structure, but suffers the drawback that it is only possible to decrease the threshold voltages slightly before forward biasing the p-n junction between the nfet and pfet back-gate wells, and thus the configuration of FIG. 5 cannot significantly reduce the threshold voltage, especially at low supply voltages. Further, the design is constrained by the diode leakage between the p and n conductive regions 540 and 542. For example, in the case where n-well bias potential is 0.6 volts less than the p-well bias potential, about 1 .mu.A per micron of leakage will be present. These drawbacks are particularly acute for standard threshold devices when it is desired to reduce the threshold to an extremely low value.